Volatile memory devices, such as dynamic and static random access memory (RAM) devices, are memory devices in which stored data may be lost as time passes. Non-volatile memory devices, such as, for example, read only memory (ROM) devices, electrically erasable and programmable ROM (EEPROM) devices and flash memory devices, are memory devices which maintain stored data over time, even when power to the device is turned off. Typically, non-volatile memory devices exhibit relatively slower data input and output speeds as compared to volatile memory devices.
In recent years, there has been increased demand for integrated circuits that combine multiple devices on a single chip. Representative examples of such devices include merged DRAM amp logic (MDL) devices that combine a DRAM cell and a logic device on a single chip, and merged flash amp logic (MFL) devices that combine a flash memory device and a logic device on a single chip.
Typically, a flash memory cell of a flash memory device has a structure that includes a floating gate, an interlayer dielectric layer, and a control gate on a semiconductor substrate. The flash memory cell may be designed so that a positive voltage that is applied to the control gate is coupled to the floating gate, and electrons in the semiconductor substrate pass through a tunnel oxide layer and are captured in the floating gate by a Fowler-Nordheim (hereinafter, referred to as “F-N”) tunneling or hot-carrier injection. The flash memory cell may be erased by applying a negative voltage to the control gate that causes the electrons in the floating gate to return to the semiconductor substrate.
Highly-integrated flash memory devices may eventually replace magnetic disk memory devices because the flash memory devices may have advantages in terms of cell area, access time and power consumption. However, current flash memory devices tend to cost more, per bit of storage, than do magnetic disk memory devices. The cost of flash memory devices may be dependent on, among other things, the number of steps in the fabrication process and the size of individual memory cells. As such, flash memory cells that have a self-aligned shallow trench isolation (hereinafter, referred to as “SA-STI”) structure have been developed as they may have reduced spacing between bit lines and therefore smaller memory cells.
FIG. 1 is a cross-sectional diagram of a flash memory cell having a conventional SA-STI structure. As shown in FIG. 1, the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 10. The silicon substrate 10 has STI regions 16 that define a plurality of active regions therebetween. Floating gates 14 are formed on the tunnel oxide layer 12, an interlayer dielectric layer 25 is formed on the floating gates 14, and a control gate 29 is formed on the interlayer dielectric layer 25. An interlayer insulating layer is formed on the control gate 29.
A polysilicon layer, for example, may be used to form the floating gates 14. This polysilicon layer may be patterned so that the floating gates 14 are formed on the active regions and on edge portions of the STI regions 16 that are adjacent the active regions.
The control gates 29 of a plurality of memory cells may be connected to form a word line. The control gates 29 may be composed, for example, of a polycide structure that includes a polysilicon layer 26 and a metal silicide layer 28, which are sequentially stacked.
In the flash memory cell of FIG. 1, data may be stored by applying appropriate voltages to the control gate 29 and the substrate 10 to inject electrons into and out of the floating gate 14. The interlayer dielectric layer 25 maintains the charge in the floating gate 14 and transfers the voltage of the control gate 29 to the floating gate 14.
The interlayer dielectric layer 25 may, for example, comprise a multi-layer structure that includes an oxide layer 20, a nitride layer 22, and a second oxide layer 24 that may have a high dielectric constant that are sequentially stacked. The first oxide layer 20 may be grown, for example, by a thermal oxidation process. The nitride layer 22 may be formed on the first oxide layer 20 by, for example, a low pressure chemical vapor deposition (LPCVD) process. The second oxide layer 24 may be grown, for example, by a thermal oxidation process.
FIGS. 2A to 2D are cross-sectional diagrams illustrating a conventional method of fabricating a non-volatile memory cell. As shown in FIG. 2A, a semiconductor substrate 10 is divided into an active region and a field region 16 by a shallow trench isolation (STI) process. This may be accomplished, for example, by etching a portion of the semiconductor substrate 10 via a trench etch process using an STI hard mask layer to form a trench. A high density plasma (HDP) oxide layer may then be deposited on the entire structure including the trench. The HDP oxide layer is etched until the STI hard mask layer is exposed so that the HDP oxide layer protrudes from the trench. Since the protruded portion of the HDP oxide layer is removed to a predetermined thickness by a wet etch, the HDP oxide layer inside the trench becomes an STI isolation layer 16. As is also shown in FIG. 2A, an oxide layer or an oxynitride layer may then be formed on the active region of the semiconductor substrate 10 to form a tunnel oxide layer (i.e., a gate oxide layer) 12.
Referring to FIG. 2B, a first polysilicon layer 14, which is used as the floating gate, is formed on the tunnel oxide layer 12 by, for example, an LPCVD process. The first polysilicon layer 14 may be formed, for example, by in-situ doping and deposition at a temperature of 600° C. or higher, or by deposition in an LPCVD chamber. A reflection prevention layer 18 (which may comprise, for example, a silicon oxynitride (SiON) layer), is formed on the first polysilicon layer 14. Then, a photoresist layer is deposited on the reflection prevention layer 18. The photoresist layer is exposed and developed to form a photoresist pattern 19 that may be used to expose a portion of the field region 16.
As shown in FIG. 2C, the reflection prevention layer 18 and the first polysilicon layer 14 above the field region 16 may be removed by a dry etch using the photoresist pattern 19 as an etch mask, thereby forming a first polysilicon layer pattern 14a that is separated from a neighboring memory cell in a word line direction (i.e., the first polysilicon layer pattern 14a extends in the same direction as does the field region 16). During the etch process of the first polysilicon layer 14, the remainder of the reflection prevention layer 18 may also be removed.
As shown in FIG. 2D, an ONO interlayer dielectric layer 25 is formed on the first polysilicon pattern 14a and the field isolation layer 16 to insulate the floating gates from a control gate.
Next, a second polysilicon layer (the second polysilicon layer is not illustrated in FIG. 2) that functions as a control gate may be deposited on the ONO interlayer dielectric layer 25. A tungsten silicide layer (also not shown in FIG. 2) may be formed on the second polysilicon layer to improve the conductivity of the control gate. The tungsten silicide layer, the second polysilicon layer, the ONO interlayer dielectric layer 25, and the first polysilicon layer pattern 14a may be dry-etched to form a memory cell having a stacked gate structure including a floating gate 14, an ONO interlayer dielectric layer 25, and a control gate 29.
As shown in FIGS. 2A to 2D, the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination. As shown in FIGS. 2C and 2D, a seam 15 may be generated inside the first polysilicon layer 14 on the active region.
FIG. 3 is a photograph illustrating a section in a conventional flash memory device having an SA-STI structure in which a seam has been generated inside the first polysilicon layer. As shown in FIG. 3, the seam 15 is located inside the first polysilicon layer of the active region. This seam may negatively impact the profile of the ONO interlayer insulating layer that is formed in a subsequent process, which may negatively impact the reliability of the device.
FIG. 4 is a photograph of the ONO interlayer dielectric layer that is formed on the first polysilicon layer of FIG. 3. As shown in FIG. 4, the ONO interlayer dielectric layer 25 has a relatively poor profile 17 as a result of the seam in the polysilicon layer.